苏州市“员工进院校--千名优秀青年职工技能提升行动”政府指定项目

“IC Compiler 2: Clock Tree Synthesis ”培养课程简介

本课程由苏州中科集成电路设计中心和Synopsys公司联合面向苏州地区企业推出。苏州市企业在职工程师参加此课程，并完成相关考核，将有机会获得政府对项目培训费用的补助。

课程内容及时间安排

Overview

In this workshop, you learn how to explore the clock tree structure through various reporting commands and how to use the CTS GUI to analyze and verify settings. The workshop goes in-depth into clock tree synthesis methodology and flows for typical 90nm and 65nm designs. You also learn how to use the log to understand the tool messages that are critical to analyzing and debugging CTS results. Reducing clock tree power and avoiding hot spots by careful clock buffer placement is covered. Finally, the basics of MCMM processing of clock trees is considered. The workshop is accompanied by comprehensive hands-on labs, which provide an opportunity to apply key concepts covered during the lectures.

Objectives

At the end of this workshop the student should be able to:

Analyze the clock tree structure prior to running CTS
Check for valid clock definitions
Use the clock options correctly
Identify good vs. bad buffers/inverters for CTS
Specify different buffers/inverters for specific optimizations within CTS
Use Non-Default Routing rules (NDR) appropriately
Describe how to perform clock shielding, how to run low power CTS Flow and use the IC Compiler CTS flows
Perform clock tree synthesis in debug mode to obtain additional tool messages
Debug QoR problems
Optimize clock power before CTS and combat thermal hot-spots by controlling clock cell spacing
Use the interactive CTS browser to analyze and debug clock structures before and after synthesis
Use MultiCorner MultiMode technology with the synthesis of the clock trees

Audience Profile

ASIC, back-end, or layout designers with experience in standard cell-based automatic Place and Route using IC Compiler.

Prerequisites

To benefit the most from the material presented in this workshop, you should:

Have taken IC Compiler 1 workshop.

Possess equivalent knowledge with IC Compiler:

Script writing using Tcl
Reading and linking a design
Using IC Compiler抯 graphical user interface (GUI)
Generating and interpreting timing reports using report_timing and report_constraint commands

Course Outline

Pre-CTS Check and Setup
Building Clock Trees
Debugging and Refining Clock Trees

Synopsys Tools Used

IC Compiler 2010.03-SP3

Time: 9:30 -12:00 13:00-17:30

师资情况介绍

朱延洲

北京工业大学硕士毕业，Synopsys全球技术支持中心资深技术支持工程师，主要支持后端工具，包括ICC等等，Synopsys全球技术支持中心中国区后端工具产品线骨干工程师，有超过6年数字集成电路后端实现以及技术支持经验，曾任职于多家著名集成电路设计公司，包括Omnivision等等。在Synopsys任职超过3年半，经验丰富。多次在Synopsys北京/上海/深圳培训中心以及北京/深圳/珠海/大连等地ICC成功主讲各种Synopsys后端工具及流程相关用户培训，学员口碑极佳。

申报条件

具有相关专业大专及以上学历，并在市区（含园区、新区）工作已建立稳定的劳动关系的企业在职工程师、项目经理等（报名时需提供相应证明材料复印件）。

课程时间及费用

课程时间：2011年2月23日。课程费用2300元/人（其中，可享受政府补助1800元/人，并可免费参加3月2日-4日的DFT Compiler 1培训课程），费用包括考证费及教材费、培训费及午餐费。

课程地点

苏州中科集成电路设计中心（苏州工业园区集成电路人才公共实训基地）培训教室：金鸡湖大道1355号国际科技园二期E401。

证书及考证

申报政府补贴学员必须通过政府主管部门组织的考试，考试合格将获得国家职业资格证书。

报名方式

单位或个人携带以下材料到苏州中科集成电路设计中心（苏州工业园区集成电路人才实训基地）报名。

报名地点：苏州工业园区金鸡湖大道1355号（原机场路）国际科技园二期E301；

联系人：邹老师 62889031 zoull@szicc.com.cn

报名材料：身份证、学历/学位证书、劳动合同、户口本（苏州市常住户口需提供）复印件，一寸近照4张。